SI4022-A0-FT【PDF 12/20 页】IC TX FSK UNI 868/915MHZ 16TSSOP

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Sheet目录57

8页 9页 10页 11页 [12页]13页 14页 15页 16页

Si4022

bit 15 14 13 12 11 10

POR

CE00h

Transmitter FIFO register write

nSEL

SCK

SDI

instruction

N data bits

filling up FIFO

N-1

N-2

Note

Note:

" If the crystal oscillator was formerly switched off (ex=0), the internal oscillator needs t

time, to switch on. The actual value depends on

the type of quartz crystal used.

" If the synthesizer was formerly switched off (es=0), the internal PLL needs t

startup time. Valid data can be transmitted only when the

internal locking process is finished.

Data Transmit Sequence Through the FSK Pin

nSEL

SCK

SDI

instruction

Internal operations

ex, es, etr = 1

xtal osc. stable

Xtal osc staus

FSK

T X D A T A

synthesizer on, PLL locked, PA ready to transmit

synthesizer / PLL /

PA status

tsx *

tsp *

C 0 h

3 8 h

d o n ' t c a r e

P o w e r M a n a g e m e n t c o m m a n d

NOTE:

* See page 5 for the timing values

FIFO Setting Command

Bit 7 <fe>:

Enables the 64 bit transmit FIFO. Resetting this bit clears the contents of the FIFO.

Bit 5-0 <f5 : f0>:

FIFO IT level. The FIFO generates IT when number of the remaining data bits in the FIFO reaches this level.

It is possible to transmit data without the FIFO by using the FSK input pin. In that case the power amplifier should be enabled first with

the Power Management Comand.

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